systemc modeling dual port memory - SERP Analysis

https://forums.accellera.org/topic/1890-model-with-multiple-target-ports/

https://developer.arm.com/documentation/102178/1102/Cycle-Model-functionality-and-operating-requirements/Functionality-of-the-SystemC-Cycle-Model

http://www.diva-portal.org/smash/get/diva2:1412164/FULLTEXT01.pdf

https://forums.ni.com/t5/LabVIEW/Model-a-dual-port-synchronous-block-RAM-with-LabVIEW-FPGA/td-p/2581473

https://repository.rit.edu/cgi/viewcontent.cgi?article=10948&context=theses

https://www.fpgarelated.com/showthread/comp.arch.fpga/86168-1.php

https://stackoverflow.com/questions/47944498/systemc-transfer-level-model-sockets-two-way-communication

https://community.intel.com/t5/FPGA-Intellectual-Property/Simultaneous-Write-Read-to-on-chip-dual-port-RAM/m-p/19286

https://www.edaboard.com/threads/testbench-system-c-symple-ram-model.238554/

https://www.accellera.org/images/downloads/standards/systemc/Accellera_SystemC_AMS_Users_Guide_January_2020.pdf

https://ieeexplore.ieee.org/document/10549556/

https://www.researchgate.net/publication/268822500_Modeling_and_Simulation_of_a_Many-core_Architecture_Using_SystemC

https://docs.amd.com/r/2022.1-English/ug1483-model-composer-sys-gen-user-guide/Dual-Port-RAM

https://www.sciencedirect.com/science/article/abs/pii/S0141933117304684

https://dvcon-proceedings.org/wp-content/uploads/designing-verifying-and-building-an-advanced-l2-cache-sub-system-using-systemc.pdf

https://aawo.dev/projects/sram-model/

https://www.ee.torontomu.ca/~courses/ee8205/Data-Sheets/systemc/System-Level-Design.pdf

https://www.asic-world.com/examples/systemc/ram_dp_ar_aw.html

https://documentation-service.arm.com/static/5f06e36180a122649b51ddb7?token=

https://www.embecosm.com/appnotes/ean1/html/ch10.html

https://ijirt.org/publishedpaper/IJIRT156065_PAPER.pdf

https://www.learnsystemc.com/basic/simu_stage

https://newport.eecs.uci.edu/~doemer/w20_eecs222/Lecture17_SystemC_Part3.pdf

https://www.renesas.com/en/products/memory-logic/multi-port-memory/asynchronous-dual-port-rams/7132-2k-x-8-dual-port-ram?srsltid=AfmBOoqzXP_C_ok0cTUnQDrK1QBf40AKUt2_RlbfnnzRDQx4DjZ18cGY

http://microelectronics.esa.int/core/ipdoc/LEON_SystemC_FinalReport.pdf

https://github.com/systemc/systemc-2.2.0/blob/master/examples/sysc/simple_bus/README

https://www.eetimes.com/fit-the-hardware-to-the-algorithm-with-systemc-models/

https://www.analog.com/en/resources/design-notes/dual-port-ram.html

https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/core-docs/Actel/SgCore/DPSRAM/sf2_dpsram_config_ug_1.pdf

https://www.ece.iastate.edu/~zambreno/classes/cpre588/documents/RosSwa05A.pdf

https://singularitykchen.github.io/blog/2020/06/29/Emulate-Transaction-Level-Modeling-in-SystemC/

https://dl.acm.org/doi/pdf/10.5555/1639809.1655403

https://jusst.org/wp-content/uploads/2021/06/Design-and-implementation-of-Dual-Port-Memory.pdf

https://www.scarpaz.com/2100-papers/systemc/00982488.pdf

https://ieeexplore.ieee.org/document/5669197/

https://staff.fnwi.uva.nl/s.polstra/psa2017/psa2017_systemc_tutorial.pdf

https://www.intel.com/content/www/us/en/docs/programmable/683562/21-3/example-converting-simple-dual-port-ram.html

https://www.doulos.com/media/1408/systemc_tutorial.pdf

https://www.edaplayground.com/x/QfhN

https://www.renesas.com/us/en/document/apn/12-using-quickswitch-make-dual-port-rams?srsltid=AfmBOorZpGJbYy1gchkU5GtE3TA-pcYz7EDeibiA7kl_OSf0nWkpASCO

https://www.diva-portal.org/smash/get/diva2:512839/FULLTEXT01.pdf

https://www.design-reuse.com/article/57965-a-fast-systemc-simulation-methodology-for-multilevel-ip-soc-design/

https://docs.amd.com/r/2024.1-English/ug1393-vitis-application-acceleration/Coding-a-SystemC-Model

https://www.cprover.org/scoot/scoot-static-scheduling-institute-seminar-oct-2009.pdf

https://hls.academy/topics/systemc-modeling/

https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=7af447a06d8ef1ffac29162411fd92ae3f4c16dc

http://media.ee.ntu.edu.tw/courses/msoc/slide/02_SystemC_Tutorial.pdf

https://mapl.cs.nycu.edu.tw/course/ESL/files/Lecture6.pdf

https://www.embedded.com/using-systemc-to-build-a-system-on-chip-platform/

https://www.youtube.com/watch?v=JglfvWS_azI

https://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG6530_RCS_html_dr/outline_W2017/docs/SYSTEMC_INFO_dr/SystemC-HS-Design.pdf

https://www.techdesignforums.com/practice/technique/parallel-simulation-of-systemc-tlm-2-0-compliant-mpsocs/

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/862421112/Co-simulation

https://www.synopsys.com/cgi-bin/proto/pdfdla/docsdl/platform_architect_ds.pdf?file=platform_architect_ds.pdf/

https://www.infineon.com/cms/en/product/gated-document/an70118-understanding-asynchronous-dual-port-rams-8ac78c8c7d718a49017d71bacdd0083c/

https://d-nb.info/1067388087/34

https://www.cs.colostate.edu/~pouchet/doc/iccad-article.15.pdf

https://web.eecs.utk.edu/~dbouldin/protected/systemc-userguide20.pdf

https://www.meity.gov.in/static/uploads/2024/03/tutorial_on_transaction_level_modeling_with_systemc_for_system_level_design-1.pdf

https://www.cadence.com/en_US/home/training/all-courses/84488.html

https://www.ece.iastate.edu/~zambreno/classes/cpre588/documents/Wal05A.pdf

https://old.gem5.org/wiki/images/a/a5/Summit2017_systemc.pdf

https://www.sciencedirect.com/science/article/pii/S2212017314004587/pdf?md5=3fcc987a7f1581c5bbfed6879fba65eb&pid=1-s2.0-S2212017314004587-main.pdf

https://intel.github.io/tsffs/simics/systemc-library/execution-of-systemc-models-in-the-simics-simulator.html

https://www.nxp.com/docs/en/application-note/AN2146.pdf

https://newport.eecs.uci.edu/~doemer/f19_ecps203/DAC15_SystemC-TLM20_Training.pdf

https://users.ece.utexas.edu/~gerstl/ece382m_f23/labs/lab3.htm

https://www.design-reuse.com/article/59061-systemc-key-modeling-concepts-besides-tlm-to-boost-your-simulation-performance/

https://agra.informatik.uni-bremen.de/doc/konf/isvlsi06_SystemExploration.pdf

https://www.ecb.torontomu.ca/~courses/ee8205/lectures/SystemC-and-Codesign.pdf

https://cs.stackexchange.com/questions/132355/two-vs-dual-port-ram

https://semiengineering.com/knowledge_centers/languages/systemc/

https://www.thecodingforums.com/threads/dual-port-ram-inference.682995/

https://comp.arch.fpga.narkive.com/k1XsOgz8/dual-port-ram-inference

https://www.electronicdesign.com/technologies/embedded/digital-ics/fpga/article/21760024/implement-abstraction-by-encapsulation-in-systemc

https://www.researchgate.net/publication/333703341_Design_and_Verification_of_Dual_Port_RAM_using_System_Verilog_Methodology

https://www.cprover.org/scoot/scoot_tacas08.pdf

https://dvcon-proceedings.org/wp-content/uploads/increasing-efficiency-and-reuse-in-modeling-systemc-tlm-ips-targeting-virtual-prototypes-for-software-development.pdf

https://inria.hal.science/hal-01466696v1/document

https://www.doulos.com/grg-exclusive/systemc-golden-reference-guide-resources/systemc-golden-reference-guide-examples/

https://caesr.uwaterloo.ca/papers/kaushik_13_systemclang.pdf

https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=bae3d87265ee90253fc4ca25bd9df5d2622a4561

https://web.eecs.utk.edu/~dbouldin/protected/systemc-tutorial.pdf

https://www-verimag.imag.fr/TR/TR-2009-7.pdf

https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/readinglist/parallel-systemc-mello-2010.pdf

https://www.embecosm.com/appnotes/ean6/embecosm-or1k-verilator-tutorial-ean6-issue-1.html

https://www.cadence.com/zh_CN/home/training/all-courses/84488.html

https://patents.google.com/patent/US8645609B2/en

https://www.scribd.com/presentation/671765043/tutorial-on-transaction-level-modeling-with-systemc-for-system-level-design

https://past.date-conference.com/proceedings-archive/2003/DATE03/DF_FILES/01D_5.PDF

https://grk2767.tu-dresden.de/files/Images/people/chair-cc/publications/1707_Menard_SAMOS.pdf

https://www.futureelectronics.com/c/semiconductors/memory--RAM--dual-ports/products

https://github.com/nvdla/sw/issues/86

https://www.youtube.com/watch?v=MYyU-bGUl-k

https://repository.rit.edu/cgi/viewcontent.cgi?referer=&httpsredir=1&article=6508&context=theses

https://www.thecodingforums.com/threads/dual-port-ram-for-beginners.23524/

https://electronics.stackexchange.com/questions/517602/pseudo-dual-port-ram-in-verilog

https://escholarship.org/content/qt8zt5p9kh/qt8zt5p9kh_noSplash_82de1a7a4746a92b3aed3e26a3e59da0.pdf

https://people.rennes.inria.fr/Chan.Ngo/pubs/SYSC.pdf