scr1 risc v - SERP Analysis

https://github.com/syntacore/scr1

https://syntacore.com/products/scr1

https://gitee.com/fog_valley_cloud/scr1

https://github.com/syntacore/scr1-sdk

https://3.opencores.org/websvn/filedetails?repname=yifive&path=%2Fyifive%2Ftrunk%2Fcaravel_yifive%2Fverilog%2Frtl%2Fsyntacore%2Fscr1%2Fdocs%2Fscr1_um.pdf

https://www.riscvschool.com/2022/08/31/scr1-risc-v-core/

https://forum.segger.com/index.php/Thread/6075-SOLVED-can-t-connect-to-Syntacore-SCR1/

https://riscv.or.jp/wp-content/uploads/syntacore_riscv_ip.pdf

https://syntacore.com/media/files/DatasheetSCR1.pdf

https://groups.google.com/a/groups.riscv.org/g/hw-dev/c/Pk0aax672H8

https://en.wikipedia.org/wiki/RISC-V

https://www.reddit.com/r/FPGA/comments/pyndj8/fpga_for_riscv_processor/

https://xml.jips-k.org/full-text/view?doi=10.3745/JIPS.03.0129

https://www.quora.com/What-advantages-does-RISC-V-architecture-offer-in-terms-of-reducing-vulnerability-to-export-controls-compared-to-x86-and-Arm-architectures

https://riscv.or.jp/wp-content/uploads/syntacore_riscv_tokyo_2021a.pdf

https://www.reddit.com/r/FPGA/comments/d4lffg/is_there_a_free_risc_v_with_axi4_and_debug/

https://kb.segger.com/Syntacore_SCR1

https://caxapa.ru/thumbs/830519/scr1_eas.pdf

https://open-src-soc.org/2022-05/media/slides/RISC-V-International-Day-2022-05-05-16h05-John-Hartley.pdf

https://www.youtube.com/watch?v=9IQxusgCiYU

https://groups.google.com/a/groups.riscv.org/g/hw-dev/c/zZxy0iFzrvI/m/LVeFiK2vAQAJ

https://www.riscvschool.com/risc-v-ip-cores/

https://www.electronicsweekly.com/news/design/eda-and-ip/risc-v-day-syntacore-risc-v-mcu-core-ip-2019-10/

https://www.youtube.com/watch?v=aIqGs8RoQKA

https://stackoverflow.com/questions/50214840/risc-v-startup-code-for-stack-pointer-initalization

https://www.youtube.com/watch?v=3PWyF-qmLfg

http://essay.utwente.nl/94048/

https://community.wolfram.com/groups/-/m/t/1400440

https://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20221212/451420.html

https://www.quora.com/Is-Risc-V-project-an-open-source-project-for-CPU-design-or-CPU-architecture-specs-Can-one-take-the-open-source-information-from-Risc-V-send-them-to-a-wafer-fab-like-TSMC-and-have-them-manufacture-own-CPU

https://open-src-soc.org/2021-03/media/slides/3rd-RISC-V-Meeting-2021-03-31-10h00-Alexander-Redkin.pdf

https://www.researchgate.net/publication/339819312_Open-Source_Validation_Suite_for_RISC-V

http://syrcose.ispras.ru/2024/submissions/SYRCoSE_2024_paper_26_36.pdf

https://cdc.cuiwah.edu.pk/Event/Project/6187

https://stackoverflow.com/questions/45912676/how-to-design-a-z-scale-cortex-m0-like-system-using-rocket-chip

https://ieeexplore.ieee.org/iel7/9022742/9027208/09027224.pdf

https://arxiv.org/pdf/2406.17878

https://forums.sifive.com/t/help-me-i-am-confused-about-risc-v-cores/2730

https://marsohod.org/projects/proekty-dlya-platy-marsokhod3/risc-v/417-hello-scr1

https://www.electronicdesign.com/markets/automation/article/21805904/the-rise-of-risc-v-on-display-at-workshop

https://hal.science/hal-04891163v1/document

https://blog.csdn.net/kuankuan02/article/details/91489378

https://eng.miet.ru/news/166475

https://repositorio.pucrs.br/dspace/bitstream/10923/26400/1/2022_2_WILLIAN_ANALDO_NUNES_TCC.pdf

https://www.youtube.com/watch?v=gX6H6b7eUMI

https://riscv.expert/media/riscv_moscow_2019/SCR1%20Tutorial%20Symposium%20Moscow.pdf

https://www.scribd.com/document/688312431/RISC-V-Resource-Constrained-Cores-a-Survey-and-Energy-Comparison

https://raw.githubusercontent.com/risclite/SuperScalar-RISCV-CPU/master/wiki/SSRV%E5%85%A8%E8%A7%A3%E6%9E%90.pdf

https://www.mehmetburakaykenar.com/is-it-worth-to-design-a-risc-v-core-from-scratch/424/

https://riscvsummit2021.sched.com/event/rmTO

https://risclite.github.io/

https://processorci.ic.unicamp.br/jenkins/job/scr1/24/console

https://2023.russianscdays.org/files/2023/pdf/RISC-V/1_Yakushkin.pdf

https://reviews.llvm.org/D140693

https://hal.science/hal-03586276/file/Extended_RISC-V_hardware_architecture_for_future_digital_communication_systems.pdf

https://se.math.spbu.ru/thesis_download?thesis_id=1347

https://gitea.auro.re/higepi/Projet_SETI_RISC-V/raw/commit/99d93a353f6289ee2bbf8dc6472ab7615b190a5a/Doc/Design_and_Implementation_of_a_RISC_V_Processor_on_FPGA.pdf

https://inspirehep.net/literature/2880607

https://anysilicon.com/risc-v-ip-cores-overview/

https://ieeexplore.ieee.org/document/9278263/

https://jnao-nu.com/Vol.%2015,%20Issue.%2001,%20January-June%20:%202024/122_online.pdf

https://www.crunchbase.com/organization/syntacore

https://www.researchgate.net/publication/381736754_NoX_a_Compact_Open-Source_RISC-V_Processor_for_Multi-Processor_Systems-on-Chip

https://www.kci.go.kr/kciportal/landing/article.kci?arti_id=ART002543367

https://marsohod.org/projects/proekty-dlya-platy-marsokhod3/risc-v/416-riscv-bootloader-compile

https://dl.acm.org/doi/abs/10.1007/s11227-023-05304-1

https://www.utupub.fi/bitstream/10024/152075/1/Myllynen_Ohto_opinnayte.pdf

https://docs.openhwgroup.org/_/downloads/cv32e40p-user-manual/en/cv32e40p_v1.8.0/pdf/

https://repos.ecosyste.ms/hosts/GitHub/topics/rv32emc

https://link.springer.com/article/10.1007/s11227-023-05304-1

https://arxiv.org/html/2406.17878v1

https://www.sigasi.com/tech/systemverilog-project-demo/

https://blog.csdn.net/gitblog_00278/article/details/142802477

https://interface.cqpub.co.jp/wp-content/uploads/if02_104.pdf

https://raw.githubusercontent.com/riscv/riscv-isa-manual/main/marchid.md

https://www.american-cse.org/csce2023-ieee/pdfs/CSCE2023-5LlpKs7cpb4k2UysbLCuOx/275900c705/275900c705.pdf

https://riscv-europe.org/summit/2024/media/proceedings/posters/25_poster.pdf

https://www.sciencedirect.com/science/article/abs/pii/S0141933118300048

https://tech-diningyo.hatenablog.com/entry/2018/09/23/185117

https://www.cmc.ca/wp-content/uploads/2021/01/Lemieux_RISCVEnablingDiversityofCPUCoresandAccelerators.pdf

https://www.hackster.io/ef/riscduino-single-core-d17324

https://se.math.spbu.ru/diplomas/theme.html?id=70

https://scholarlypublications.universiteitleiden.nl/access/item%3A3633958/download

https://alvinrolling.github.io/risc-v/RISCV-IP-Vendor/

https://www.scribd.com/document/431035752/Open-Source-RISC-V-Cores

https://foss-eda-tools.googlesource.com/third_party/shuttle/sky130/mpw-007/slot-006/%2B/4f03b18e1172f762f0250e3e1cf052bc4ef80857

https://repos.ecosyste.ms/hosts/GitHub/owners/dominiksalvet?order=desc&sort=pushed_at

https://www.theregister.com/2021/07/15/yadro_riscv/

https://upcommons.upc.edu/bitstream/handle/2117/357053/160243.pdf?sequence=1

https://www.youtube.com/watch?v=CJIcUezLs64

https://lampiao.ic.unicamp.br/jenkins/job/scr1/56/execution/node/3/ws/scr1/dependencies/riscv-tests/isa/rv32ui

https://gitee.com/funzero/riscv-cores-list

https://ebics.net/russia-bets-on-risc-v-as-its-semiconductor-industry-is-on-the-brink-of-extinction/

https://riscv.expert/media/riscv_moscow_2019/riscv_sw_upd.pdf

https://cnrv.io/bi-week-rpts/2017-07-20

https://platform.efabless.com/projects/670

https://cds.cern.ch/record/2927327/files/document.pdf

https://www.hackster.io/ef/riscduino-dual-core-6b64a0

https://tech-diningyo.hatenablog.com/entry/2018/08/12/222405