model hw cache with timing in systemc tlm - SERP Analysis

https://users.ece.utexas.edu/~gerstl/publications/iess09.cache.pdf

https://forums.accellera.org/topic/6329-systemc-performance/

https://www.mathworks.com/help/hdlverifier/ug/loosely-timed-systemc-tlm-simulation.html

https://www.accellera.org/images/downloads/standards/systemc/TLM_2_0_LRM.pdf

http://www.diva-portal.org/smash/get/diva2:1412164/FULLTEXT01.pdf

https://link.springer.com/chapter/10.1007/978-3-642-04284-3_9

https://www.mathworks.com/help/hdlverifier/ug/untimed-systemc-tlm-simulation.html

https://documentation-service.arm.com/static/5f06e36180a122649b51ddb7?token=

https://mediatum.ub.tum.de/doc/1237691/1237691.pdf

https://hal.science/hal-00761047v1/document

https://past.date-conference.com/proceedings-archive/2010/DATE10/PDFFILES/09.2_3.PDF

https://embecosm.com/appnotes/ean1/ean1-tlm2-or1ksim-2.0.html

http://microelectronics.esa.int/core/ipdoc/LEON_SystemC_FinalReport.pdf

https://socrocket.github.io/mmu_cache_p.html

https://newport.eecs.uci.edu/~doemer/w19_eecs222/resources/TLM_2_0_requirements.pdf

https://www.sciencedirect.com/science/article/pii/S0045790623002276

https://dvcon-proceedings.org/wp-content/uploads/designing-verifying-and-building-an-advanced-l2-cache-sub-system-using-systemc.pdf

https://www.arteris.com/learn/simulation-modeling/

https://www.date-conference.com/proceedings-archive/2017/pyear/PAPERS/2012/DATE12/PDFFILES/03.2_1.PDF

https://www1.chapman.edu/~arasteh/publications/FSE_TR_23_01.pdf

https://llvm.org/pubs/2008-03-DATE-TLM_Estimation.pdf

http://slam.ece.utexas.edu/pubs/ESLSyn13.cache.pdf

https://www.mdpi.com/2079-9292/7/5/75

https://www.tu-chemnitz.de/informatik/CAS/publications/pdfs/Masrur2010d.pdf

https://cecs.uci.edu/files/2023/01/CECS-TR-22-04.pdf

http://www.diva-portal.org/smash/get/diva2:1205337/FULLTEXT01.pdf

https://www.researchgate.net/figure/Processor-TLM-organization-with-cache-model_fig1_221448366

https://dvcon-proceedings.org/wp-content/uploads/Unified-Functional-and-Performance-Framework-A-Case-Study-of-Cache-Using-SystemC-TLM-Non-Blocking-Interfaces.pptx

https://escholarship.org/content/qt40b4s14p/qt40b4s14p.pdf

https://xn--m1bdba5a7gresc7dsa.xn--11b7cb3a6a.xn--h2brj9c/writereaddata/files/Novel_Approach_for_Cache_Memory_Simulation.pdf

https://dl.acm.org/doi/10.1145/3607548

https://www.scribd.com/document/306848726/SystemC-TLM

https://llvm.org/pubs/2009-01-ASP-DAC-MemorySimulation.pdf

https://www1.chapman.edu/~arasteh/publications/DATE_24.pdf

https://www.ideals.illinois.edu/items/93200/bitstreams/303413/data.pdf

https://dl.acm.org/doi/pdf/10.5555/1509633.1509814

https://builders.intel.com/docs/wp_system_arch_exploration_using_simics_0810.pdf

https://jes-eurasipjournals.springeropen.com/counter/pdf/10.1155/2007/71043.pdf

https://hal.science/hal-01292317/document

https://www.researchgate.net/figure/Speed-up-comparison-TLM-vs-CA-SystemC_fig5_282806593

https://amstel.estec.esa.int/tecedm/website/biblio/FossatiSocrocket2013.pdf

https://www.irisa.fr/archi09/pecheux.pdf

https://old.gem5.org/wiki/images/a/a5/Summit2017_systemc.pdf

https://arxiv.org/pdf/2505.12987

https://www.mirabilisdesign.com/doc_files/doc/CodeDoc/WebHelp/VisualSimDocs/SystemCTLM20Example.html

https://github.com/Xilinx/libsystemctlm-soc/blob/master/docs/ace-rtl-bridges/tlm/bridges.md

https://d3pcsg2wjq9izr.cloudfront.net/files/10663/download/668757/1-3.pdf

http://publications.rwth-aachen.de/record/728315/files/728315.pdf

https://ieeexplore.ieee.org/document/6513720/

https://www.irisa.fr/archi09/joloboff.pdf

https://www.embecosm.com/appnotes/ean6/embecosm-or1k-verilator-tutorial-ean6-issue-1.html

https://cris.unibo.it/retrieve/e1dcb338-a1d9-7715-e053-1705fe0a6cc9/GVSOC_ICCD_2021_redux.pdf

https://www.eetimes.com/a-systemc-tlm-based-methodology-for-ip-development-and-fpga-prototyping/

https://lup.lub.lu.se/student-papers/record/9043431/file/9043432.pdf

https://ics.jku.at/files/2020DATE_Fast_and_Accurate_Performance_Evaluation_RISC-V_VPs.pdf

https://www.embedded.com/using-systemc-to-build-a-system-on-chip-platform/

https://hvg.ece.concordia.ca/Publications/Conferences/02_SETIT%2707.pdf

https://www.ocpip.org/images/downloads/standards/systemc/TLM2_Whitepaper.pdf

https://www.ovpworld.org/documents/OVPsim_Using_OVP_Models_in_SystemC_TLM2.0_Platforms.pdf

https://link.springer.com/article/10.1007/s10766-018-0566-x

https://developer.arm.com/ja/tools-and-software/simulation-models/fast-models?sc_lang=en

https://www.arteris.cn/resources/

https://par.nsf.gov/servlets/purl/10192408

https://www.cse.scu.edu/~m1wang/verification/Model.pdf

https://www.design-reuse.com/article/59818-tlm-2-0-standard-into-action-designing-efficient-processor-simulators-/

http://production.datastore.cvt.dk/oafilestore?oid=5a86ca9e5010df651b6f74b7&targetid=5a86ca9e5010df651b6f74b9

https://www.cl.cam.ac.uk/research/srg/han/ACS-P35/documents/TLM_2_0_user_manual.pdf

https://research.tue.nl/files/46955402/656541-1.pdf

https://www.gem5.org/about/

https://eprint.iacr.org/2025/589.pdf

https://www.meity.gov.in/static/uploads/2024/03/tutorial_on_transaction_level_modeling_with_systemc_for_system_level_design-1.pdf

https://www.cadence.com/en_US/home/resources/white-papers/how-the-productivity-advantages-of-high-level-synthesis-can-improve-ip-design-verification-and-reuse-wp.html

https://www.bib.irb.hr:8443/633627/download/633627.05656342.pdf

https://arxiv.org/html/2505.10145v1

https://www.sciencedirect.com/topics/computer-science/systemc

https://www.cprover.org/cbmc/applications/

https://onlinelibrary.wiley.com/doi/10.1155/2020/2567915

https://www.ovpworld.org/modeldocs/OVP_Guide_To_Using_Processor_Models.pdf

https://hpc.pnl.gov/SEAK/files/DAC_2014_files/posters/ColumbiaUniversity.pdf

https://www.arm.ecs.soton.ac.uk/wp-content/uploads/sites/360/2016/10/gem5_tutorial.pdf

https://github.com/dcblack/sc-platform

https://www.chciken.com/simulation/2023/11/11/par-gem5.html

https://www.academia.edu/2964859/System_platforms_based_systemC_TLM_design_of_image_processing_chains_for_embedded_applications

https://ieeexplore.ieee.org/iel5/11014/34699/01656857.pdf

https://publica.fraunhofer.de/bitstreams/03f5f264-3cf9-427e-a397-cdb7f5fed4ef/download

https://etheses.whiterose.ac.uk/id/eprint/1088/1/combined_-_3rd.pdf

https://www.techdesignforums.com/practice/technique/get-most-system-architectures/

https://slideplayer.com/slide/14031069/

https://www.scribd.com/presentation/671765043/tutorial-on-transaction-level-modeling-with-systemc-for-system-level-design

https://www.amd.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2020_2/ug902-vivado-high-level-synthesis.pdf

https://singularitykchen.github.io/blog/tags/

https://www.academia.edu/21387257/RTOS_modeling_in_SystemC_for_real_time_embedded_SW_simulation_A_POSIX_model

https://picture.iczhiku.com/resource/eetop/ShkwRuysrUiGsXvM.pdf